The Realtek RTL8185L, fully complying with IEEE 802.11a/b/g specifications, is a low-profile highly integrated cost-effective Wireless LAN network interface controller that integrates a Wireless LAN MAC and a Direct Sequence Spread Spectrum (DSSS) baseband processor onto one chip. To reduce protocol overhead, the RTL8185L supports Short InterFrame Space (SIFS) burst mode to send packets back-to-back. A protection mechanism prevents collisions among 802.11b nodes.
The RTL8185L implements Direct Sequence Spread Spectrum (DSSS), Complementary Code Keying (CCK), and Orthogonal Frequency Division Multiplexing (OFDM) baseband processing to support all IEEE 802.11a, 802.11b, and 802.11g data rates. Differential phase shift keying modulation schemes, DBPSK and DQPSK with data scrambling capability, are available, along with complementary code keying to provide data rates of 1, 2, 5.5, and 11Mbps, with long or short preamble. A high speed Fast Fourier Transform (FFT)/Inverse Fast Fourier Transform (IFFT), combined with BPSK, QPSK, 16QAM and 64QAM modulation of the individual subcarriers, provides data rates of 6, 9, 12, 18, 24, 36, 48 and 54Mbps, with rate compatible punctured convolutional coding with a coding rate of 1/2, 2/3, and 3/4. When in Realtek Turbo Mode, the RTL8185L provides a data rate of 72Mbps.
The RTL8185L builds in an enhanced signal detector, an adaptive frequency domain equalizer, and a soft-decision Viterbi decoder to alleviate severe multipath effects. Efficient IQ-imbalance calibration, DC offset, phase noise, frequency offset, and timing offset compensation are provided for the radio frequency front-end impairments. Selectable digital transmit and receiver FIR filters are provided to meet the requirements of transmit spectrum masks, and to reject adjacent channel interference, respectively. Both in the transmitter and receiver, programmable scaling in the digital domain trades the quantization noise against the increased probability of clipping. Robust signal detection, symbol boundary detection, and channel estimation perform well at the minimum sensitivity.
The RTL8185L supports fast receiver Automatic Gain Control (AGC) and antenna diversity functions, and an adaptive transmit power control function to obtain better performance in the analog portions of the transceiver. It also has on-chip digital-to-analog converters and analog-to-digital converters for analog I and Q inputs and outputs, transmit TSSI and receiver RSSI input, and transmit and receiver AGC outputs.
It supports Advanced Configuration Power management Interface (ACPI), PCI power management for modern operating systems that are capable of Operating System directed Power Management (OSPM).
In addition to the ACPI feature, the RTL8185L also supports remote wake-up (including AMD Magic Packet and Microsoft® wake-up frame) in both ACPI and APM environments. The RTL8185L is capable of performing an internal reset through the application of auxiliary power. When auxiliary power is applied and the main power remains off, the RTL8185L is ready and waiting for a Magic Packet or wake-up frame to wake the system up. Also, the LWAKE pin provides four different output signals including active high, active low, positive pulse, and negative pulse. The versatility of the RTL8185L LWAKE pin provides motherboards with Wake-On-LAN (WOL) functionality.
PCI Vital Product Data (VPD) is also supported to provide the information that uniquely identifies hardware (i.e., the RTL8185L LAN card). The information may consist of part number, serial number, and other detailed information.
The RTL8185L supports an enhanced link list descriptor-based buffer management architecture, which is an essential part of a design for a modern network interface card. It contributes to lowering CPU utilization. Also, the RTL8185L boosts its PCI performance by supporting PCI Memory Read Line & Memory Read Multiple when transmitting, and Memory Write and Invalidate when receiving.
The RTL8185L keeps network maintenance costs low and eliminates usage barriers. The RTL8185L is highly integrated and requires no 'glue' logic or external memory.
- 128-Pin E-pad TQFP
- State machine implementation without external memory (RAM, flash) requirement
- Complies with IEEE 802.11a/b/g standards
- Supports descriptor-based buffer management
- Integrated Wireless LAN MAC and Direct Sequence Spread Spectrum/OFDM Baseband Processor in one chip
- Enhanced signal detector, adaptive frequency domain equalizer, and soft-decision Viterbi decoder to alleviate severe multipath effects
- Processing Gain compliant with FCC
- On-Chip A/D and D/A converters for I/Q Data, AGC, and Adaptive Power Control
- Targets Multipath Delay Spreads of 125ns at 11Mbps
- Supports both transmit and receive Antenna Diversity
- Data rates of 1, 2, 5.5, 6, 9, 11, 12, 18, 24, 36, 48, and 54Mbps. Turbo mode supports 72Mbps
- Supports CardBus. The CIS can be stored in a 93C56
- Supports 40MHz OSC as the internal clock source. The frequency deviation of OSC must be within 25 PPM on IEEE 802.11g and 20 PPM on IEEE 802.11a
- Complies with PC97, PC98, PC99, and PC2001 standards
- PCI local bus network interface controller
- Complies with PCI Revision 2.2 and MiniPCI Revision 1.0
- PCI power management Revision 1.1
- PC Card Revision 8.2
- Supports PCI clock 20MHz~36MHz
- Supports PCI target fast back-to-back transactions
- Supports Memory Read Line, Memory Read Multiple, Memory Write and Invalidate
- Provides PCI bus master data transfers and PCI memory space or I/O space mapped data transfers of the RTL8185L’s operational registers
- Supports PCI VPD (Vital Product Data)
- Supports ACPI, PCI power management
- Supports Wake-On-LAN (WOL) function and remote wake-up (Magic Packet and Microsoft® wake-up frame)
- Supports 4 WOL signals (active high, active low, positive pulse, and negative pulse)
- Supports auxiliary power auto-detect, and sets the related capability of power management registers in PCI configuration space
- IEEE 802.11g protection mechanisms for both RTS/CTS and CTS-to-self
- Burst-mode support for dramatically enhanced throughput
- Supports jumbo frames
- DSSS with DBPSK and DQPSK, CCK modulations and demodulations supported with long and short preamble
- OFDM with BPSK, QPSK, 16QAM and 64QAM modulations and demodulations supported with rate compatible punctured convolutional coding with coding rate of 1/2, 2/3, and 3/4
- Efficient IQ-imbalance calibration, DC offset, phase noise, frequency offset and timing offset compensation reduce analog front-end impairments
- Selectable digital transmit and receiver FIR filters provided to meet transmit spectrum mask requirements and to reject adjacent channel interference
- Programmable scaling both in transmitter and receiver to trade quantization noise against the increased probability of clipping
- Fast receiver Automatic Gain Control (AGC) & antenna diversity functions
- Adaptive transmit power control function
- Hardware-based IEEE 802.11i encryption/decryption engine, including 64-bit/128-bit WEP, TKIP, and AES
- Programmable PCI burst size for both read and write commands
- Supports a 32-bit general-purpose timer with the external PCI clock as clock source
- Contains two large independent transmit and receive FIFO buffers
- Advanced power saving mode when the LAN and wakeup function are not used
- Uses 93C46 (64*16-bit EEPROM) or 93C56 (128*16-bit EEPROM) to store resource configuration, ID parameter, and VPD data
- LED pins for various network activity indications
- Two GPIO pins supported
- Supports digital loopback capability on both ports
- Flexible RF transceiver interface for different RF transceiver applications
- Scatter and gather operation
- 3.3V and 1.8V power supplies required
- 5V tolerant I/Os
- 0.18μm CMOS process