The RTL8954C/RTL896xC products are integrated System-on-a-Chip (SoC) Application Specific Integrated Circuits (ASIC) Gigabit Ethernet VoIP Controllers that implement a L2 switch, L3 routing, and L4 NAT functions. An RLX5281 CPU is embedded and the clock rate can be up to 620MHz. To improve computational performance, a 16 Kbyte I-Cache, 8-Kbyte D-Cache, 40-Kbyte I-MEM, and 8-Kbyte D-MEM are provided. A standard 5 signal P1149.1 compliant EJTAG test interface is supported for CPU testing and software development.

Via table configuration and look-up, the RTL8954C/RTL896xC products can perform hard-wired network traffic forwarding. The CPU may be used to handle upper layer functions, such as DHCP, HTTP, and some other protocols, and to operate with a hard-wired forwarding engine.

The RTL8954C/RTL896xC products provide six ports (from port 0 to port 5), integrated with six Gigabit Ethernet MACs and five physical layer transceivers for 10Base-T, 100Base-TX, and 1000Base-TX. Each port of the RTL8954C/RTL896xC products may be configured as a LAN or WAN port. Port 5 supports an external MAC interface that could be an GMII/RGMII/MII interface type to work with an external MAC or PHY transceiver.

The RTL8954C/RTL896xC products supports flexible IEEE 802.3x full-duplex flow control and optional half-duplex backpressure control. For full-duplex, standard IEEE 803.3x flow control will enable pause ability only when both sides of UTP have auto-negotiation ability and have enabled pause ability. The RTL8954C/RTL896xC products also provide optional forced mode IEEE 802.3x full-duplex flow control. Based on optimized packet memory management, the RTL8954C/RTL896xC products are capable of Head-Of-Line blocking prevention.

Due to there powerful protocol parser, the RTL8954C/RTL896xC products can recognize and hard-wire-forward VLAN-tagged, SNAP/LLC, PPPoE, IP, TCP, UDP, ICMP, IGMP, and PPTP packets. Layer 2, 3, and 4 information is stored in look-up tables. For VLAN and PPPoE protocols, the RTL8954C/RTL896xC products can automatically encapsulate and decapsulate VLAN tagged frames and PPPoE headers.

L2 Switch Features: The RTL8954C/RTL896xC products contain a 1024-entry address look-up table with a 10-bit 4-way XOR hashing algorithm for address searching and learning. Auto-aging of each entry is provided and the aging time is around 300~450 seconds.

L3 Routing Features: An 8-entry long-prefix-matching IP CAM (Content Addressable Memory) is provided to support seven CIDR (Classless InterDomain Routing) subnets and one default route. For ARP entries, a 512-entry table is provided for subnet host addresses.

L4 Processing Features: The RTL8954C/RTL896xC products contains a 1024-entry Network Address Port Translation (NAPT) table for address translation. The Layer 4 port (TCP/UDP) or ICMP ID can be auto-learnt if an empty entry is encountered. To improve table utilization efficiency, auto-aging according to protocol, and auto-deletion based on TCP flags or timeout are both provided.

In addition to L2/L3/L4 processing, in order to fulfill the needs of a firewall gateway, the RTL8954C/RTL896xC products also provide an Access Control List (ACL) rule table to filter packets. The ACL rules are also attached to Network Interface tables. The filtering parameters are configurable and include MAC addresses, Layer 3, Layer 4 protocol information, etc. The RTL8954C/RTL896xC products contains a protocol-parsing table to trap user-defined packets to the embedded CPU for further processing.

To improve multimedia and real-time networking applications, the RTL8954C/RTL896xC products support five types of QoS. They are based on:
(1) Port-based priority
(2) 802.1p/Q VLAN priority tags
(3) TCP/IP’s TOS/DS (DiffServ) field
(4) ACL (Access Control List) rules
(5) NAT-table-based

Six-level output queues are also provided to support QoS (Per-port support for 6 priority queues).

The RTL8954C/RTL896xC products support port-based, protocol-based, and tagged VLANs. Up to four thousand VLAN groups can be assigned. VLAN tags are inserted or removed based on the VLAN table configuration. The spanning tree protocol is supported and the states are divided into four types: Disabled, Blocking/Listening, Learning, and Forwarding.

The RTL8954C/RTL896xC products support one set per-port of MIB counters that include MIB-II (RFC 1213), Ethernet-like MIB (RFC 3635), Interface Group MIB (RFC 2863), RMON MIB group 1, 2, 3, 9 (RFC 2819), Bridge MIB (RFC 1493), and Bridge MIB Extension (RFC 2674).

The RTL8954C/RTL896xC products provide bandwidth and packet scheduling functions. Ingress and Egress port bandwidth control functionality can limit the bandwidth of a port to between 16Kbps and 1Gbps, with support for scaled solutions, e.g., 16Kbps (ingress)/64Kbps (egress). The packet scheduling function provides each output queue with 2 leaky buckets, and each output port with one leaky bucket mechanism to control bandwidth scheduling based on the packet’s QoS priority information.

To prevent broadcast storm attacks, the Broadcast Storm Control function is supported and provides a configurable broadcast utilization load.

For peripheral interfaces, two 16550-compatible UARTs are supported, and a 16-byte FIFO buffer is provided. A USB 2.0 host controller is embedded in the RTL8954C/RTL896xC products to provide EHCI and OHCI 1.1 compliant host functionality. In addition, a USB PHY has been embedded in the RTL8954C/RTL896xC products.

An MDI/MDIX auto crossover function is supported. For accessing high-speed devices, the RTL8954C/RTL896xC products provides a PCI Express host and a PCI Express slave to access a PCI Express interface.

The RTL8954C/RTL896xC products require only a single 25MHz crystal or 40MHz clock input for the system PLL. The RTL8954C/RTL896xC products also have two hardware timers and one watchdog timer to provide accurate timing and watchdog functionality. For extension and flexibility, the RTL8954C/RTL896xC products have up to 44 GPIO pins.

The RTL8954C/RTL896xC products are provided in a 216-Lead Thermally Enhanced Low Profile Plastic Quad Flat Package (LQFP216 E-PAD). It requires only a 3.3V and 1.0V external power supply.

• Embedded RISC CPU, RLX5281 with 16KB I-Cache, 8KB D-Cache, 40KB I-MEM, and 8KB D-MEM
• Supports Radiax DSP Extension ISA
• Supports MIPS-1 ISA, MIPS16 ISA
• Clock rate up to 620MHz
• Provides a standard 5-signal P1149.1 EJTAG test port
• Supports RLX5281 CPU suspend mode

• Six Gigabit Ethernet MAC switch with five IEEE 802.3 10/100/1000Mbps physical layer transceivers
• Supports 1 dedicated GMII/RGMII/MII port to connect to an external MAC or PHY (supports both PHY mode and MAC mode) for HomePlug or HomePNA applications on the RTL8954C/RTL896xC products
• Non-blocking wire-speed reception and transmission and non-head-of-line-blocking/forwarding
• Internal 512Kbit SRAM for packet buffering
• Internal 1024 entry 4-way hash L2 look-up table
• Supports source and destination MAC address filtering
• Supports Broadcast Storm Control with configurable storm load utilization
• Supports 4k-entry VLAN table
• Supports port-based, protocol-based, and tagged VLANs
• Supports 802.1Q VLAN Tag aware or unaware configuration modes
• Supports IEEE 802.1x port-based and MAC-based Network Access Control
• Complies with IEEE 802.3/802.3u/802.1q/802.1d
• Flexible full-duplex 802.3x flow control and optional half-duplex backpressure flow control
• MAC learning supports Shared VLAN Learning (SVL) and Independent VLAN Learning (IVL) modes
• Three LED indicators per port for link, speed, full/half duplex
• Bi-color LED display mode

• Supports 8-entry IPv4 routing table and longest-prefix-matching table lookup
• Supports 8 PPPoE sessions simultaneously
• Supports configurable automatic PPPoE encapsulation and decapsulation
• Supports hardware 512-entry ARP table for host IP addresses
• Supports IPv4 checksum auto-check and auto-generation

• Supports 1024-entry 4-way L4 hash table for wire-speed Network Address Port Translation (NAPT) for TCP/UDP protocols
• Supports both 3-tuple and 5-tuple hashing algorithm for NAPT lookup
• Supports hardware and software NAPT interaction interface
• Supports TCP three-stage aging mechanism to trace the TCP connection and to improve table utilization
• Automatic L4 TCP/UDP checksum check and generation

• Supports 128 hardware Access Control List rules
• Supports per subnet interface ingress and egress ACL filtering
• Supports field filtering for Ethernet, PPPoE, TCP, UDP, ICMP, and IGMP protocols

• Each port supports 6-level output for QoS application. Packet priority can be decided based on Port, 802.1p tag, DSCP, ACL-based priority, and NAT-based priority
• Ingress Bandwidth Control with 16kbps configuration scale resolution
• Output queue Min-Max2 leaky bucket QoS architecture and WFQ (Weighted Fair Queue) packet scheduling capability
• Egress bandwidth control supports 64kbps scale resolution
• IEEE 802.1p and DSCP priority remarking capability

• Supports BSD mbuf-like packet structure with adjustable cluster size (128-byte to 2Kbyte) to provide optimum memory utilization
• Supports auto L3/L4 Checksum check and re-generation
• Provides the ‘To-CPU reason’ in the packet header to facilitate packet processing
• The NIC DMA support multiple-descriptor-ring architecture for QoS applications (supports 6 RX descriptor rings and 2 TX descriptor rings)

• Supports one PCI Express Host and one PCI Express Slave
• Two PCI Express PHY embedded
• Supports one USB 2.0 host controller for access to USB-supported peripherals
• One USB PHY is embedded
• Supports two 16550 UARTs
• Supports up to 44 GPIO pins Memory Interfaces
• Serial Flash (SPI Type)
  • Supports two banks and dual I/O channels for SPI Flash application
  • Each Flash bank can be configured as 256k/512k/1M/2M/ 4M/8M/16Mbytes
  • Boot up from SPI flash is supported
• SDR DRAM
  • Supports two SDR DRAM banks; each can be configured as 2M/4M/8M/16M/32M/64Mbyte
  • 16-bit SDR DRAM data bus supported. System totally supports up to 128Mbyte SDR DRAM memory space
• DDR1 DRAM
  • Supports one DDR1 DRAM bank that can be configured as 16/32/64/128Mbytes
  • 16-bit DDR1 DRAM data bus supported. System totally supports up to 128Mbyte DDR1 DRAM memory space

DDR2 DRAM

• Supports one DDR2 DRAM bank that can be configured as 32M/64/128Mbyte
• 16-bit DDR2 DRAM data bus supported. System totally supports up to 128Mbyte DDR2 DRAM memory space

MIB Counter

• Each port supports MIB counters, including MIB-II (RFC 1213), Ethernet-like MIB (RFC 3635), Interface Group MIB (RFC 2863), RMON MIB group 1, 2, 3, 9 (RFC 2819), Bridge MIB (RFC 1493), and Bridge MIB Extension (RFC 2674)

Supports Green Ethernet

• Cable length power saving
• Link Down Power Saving

Supports pre-IEEE 802.3az Energy Efficient Ethernet (EEE) for 1000Base-T and 100Base-TX in full duplex operation, and 10Base-T in full/half duplex mode
PCM Interface

• Supports 8 PCM channels for VoIP applications
• Supports 8-bit -law/A-law companding and 16-bit linear mode

I2S Interface

• Sample bit: 16 bit
• Sample rate: 8K, 16K, 24K, 32K, 48K, 96K
• IIS channel num: mono
• Max page_num = 4 Max page_size =16K byte
• Supports Mono TX or RX or TX&RX mode

Other Add-on-Value Features

• Supports Link Down Power Saving in Ethernet PHYceivers
• Supports two hardware timers and one watchdog timer
• Supports Non-Flash Booting Interface (NFBI)
• Per-port configurable auto-crossover function
• Built-in regulator controller
  • DDR1 DRAM to transform 3.3V to 2.5V via an external BJT transistor
  • DDR2 DRAM to transform 3.3V to 1.8V via an external BJT transistor
• Single 25MHz crystal or 40MHz clock input
• LQFP216 E-PAD Package