The RTL8366S and RTL8366SR are 164/216-pin, low-power, high-performance 5+1-port Gigabit Ethernet switches, with integrated 5-port Giga-PHY that supports 1000Base-T, 100Base-T, and 10Base-T, and with one extra GMII/MII/RGMII port for specific applications. They integrate all the functions of a high-speed switch system; including SRAM for packet buffering, non-blocking switch fabric, and internal register management into a single 0.13µm CMOS device. Only a 25MHz crystal is required; an optional EEPROM is offered for internal register configuration.
The embedded packet storage SRAM in the RTL8366S(R) features superior memory management technology to efficiently utilize memory space. The RTL8366S(R) integrates a 1K-entry look-up table with a 10-bit 4-way XOR Hashing algorithm for address searching and learning. The table provides read/write access from the EEPROM Serial Management Interface (SMI), and each of the entries can be configured as a static entry. The entry aging time is between 200 and 400 seconds. Eight Filtering Databases are used to provide Independent VLAN Learning and Shared VLAN Learning (IVL/SVL) functions.
The 5th port MAC or PHY of the RTL8366S and RTL8366SR implement dual MII/RGMII interfaces (the 6th port MAC of the RTL8366SR provides a single GMII interface) for connecting with an external PHY or MAC in specific applications. This interfaces could be connected to an external CPU or RISC as 5-port Gigabit Router applications. In router applications, the RTL8366S(R) supports Port VID (PVID) for each port to insert a PVID in the VLAN tag on egress. When using this function, VID information carried in the VLAN tag will be changed to PVID.
The RTL8366S(R) supports standard 802.3x flow control frames for full duplex and optional backpressure for half duplex. It determines when to invoke the flow control mechanism by checking the availability of system resources, including the packet buffers and transmitting queues. The RTL8366S(R) supports broadcast/multicast output dropping, and will forward broadcast/multicast packets to non-blocked ports only. For IP multicast applications, the RTL8366S(R) supports IPv4 IGMPv1/v2/v3 and IPv6 MLDv1/v2 snooping.
In order to support flexible traffic classification, the RTL8366S(R) supports 32-entry ACL rule check and multiple actions options. Each port can optionally enable or disable the ACL rule check function. The ACL rule key can be based on packet ingress port, destination/source MAC address, 802.1q VID, 802.1q PRI, EtherType field, destination/source IP address, destination/source port number (TCP and UDP), ICMP, and IGMP. When an ACL rule matches, the action taken is configurable to Drop/Permit/Redirect/Mirror, change priority value in 802.1q/Q tag, and rate policing. The rate policing mechanism supports from 64Kbps to 1Gbps (in 64Kbps steps)
In Bridge operation the RTL8366S(R) supports 8 sets (based on Filtering Database) of port configurations: disable, block, learning, and forwarding for Spanning Tree Protocol and Multiple Spanning Tree Protocol. To meet security and management application requirements, the RTL8366S(R) supports IEEE 802.1x Port-based/MAC-based Access Control. For those ports that do not pass IEEE802.1x authentication, the RTL8366S(R) provides a Port-based/MAC-based Guest VLAN function for them to access limited network resources. A 1 set Port Mirroring function is configured to mirror traffic (RX, or TX, or both) appearing on one of the switch’s port. Support is provided on each port for many RFC MIBs Counters easy debug and diagnostics.
To improve real-time or multimedia networking applications, the RTL8366S(R) supports four priority-assignments for each received packet. These are based on (1) Port based priority; (2) 802.1p/Q VLAN tag priority; (3) DSCP field in IPv4/IPv6 header; and (4) ACL-assigned priority. Each output port supports a weighted ratio of four priority queues to fit bandwidth requirements in different applications. The input bandwidth control function helps limit per-port traffic utilization. There are 2 leaky buckets for each queue of all ports, one for Average packet rate control and the other for Peak packet rate control. Queue scheduling algorithm can use Strict Priority (SP) or Weighted Fair Queue (WFQ) or mixed.
The RTL8366S(R) provides a 4K-entry VLAN table for 802.1Q port-based, tag-based, and protocol-based VLAN operation to separate logical connectivity from physical connectivity. The RTL8366S(R) supports four Protocol-based VLAN configurations that can optionally select EtherType, LLC, and RFC1042 as the search key. Each port may be set to any topology via EEPROM upon reset, or EEPROM SMI Slave after reset. The RTL8366S(R) also provides options to meet special VLAN application requirements. The first option is the ARP VLAN function, which is used to select to broadcast ARP frames to all VLANs, or only forward ARP frames to the originating VLAN. The second option is the Leaky VLAN function, which sends unicast frames to other VLANs, or only forwards unicast frames to the originating VLAN. The VLAN tags can be inserted or removed on a per-port basis.
In router applications, the router may want to know the input port of the incoming packet. The RTL8366S(R) supports an option to insert a VLAN tag with VID=Port VID (PVID) on each egress port. The RTL8366S(R) also provides an option to admit VLAN tagged packet with a specific PVID only. If this function is enabled, the RTL8366S(R) will drop all non-tagged packets and packets with an incorrect PVID.
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- Single-chip 5+1-port gigabit non-blocking switch architecture
- Embedded 5-port 10/100/1000Base-T PHY
- Each port supports full duplex 10/100/1000M connectivity (half duplex only supported in 10/100M mode)
- IEEE 802.3x flow control
- 832Kbits SRAM for packet buffer
- Supports maximum packet length 16Kbyte jumbo frame packet forwarding and maximum packet length 9216 bytes at wire speed
- Supports Realtek Cable Test (RTCT) function
- RTL8366SR (only) Extra Interface (5th port MAC or PHY, and 6th port MAC) supports:
- Media Independent Interface (MII)
- Gigabit Media Independent Interface (GMII) (1000Mbps only)
- Reduced Gigabit Media Independent Interface (RGMII)
- Port 4 supports 1000Base-X SerDes or UTP
- Supports 32-entry ACL Rules
- Search keys support Source Port, MAC, TCP, UDP, IPv4, IPv6, ICMP, and IGMP format
- Actions support mirror, redirect, dropping, priority adjustment, and traffic rate policing
- Optional per-port enable/disable of ACL function
- Optional setting of per-port action to take when ACL mismatch
- VLAN
- 802.1Q VLAN supports for 4096 entries
- Supports Port-based, Tag-based, and Protocol-based VLAN
- Up to 4 Protocol-based VLAN entries
- Supports per-port and per-VLAN egress VLAN tagging and un-tagging
- Supports IVL/SVL
- Supports 1K-entry MAC address table with 4-way hash algorithm
- Supports 8-entry CAM to avoid learning hash collisions
- Up to 8 Filtering Databases
- Supports Spanning Tree port behavior configuration
- IEEE 802.1w Rapid Spanning Tree
- IEEE 802.1s Multiple Spanning Tree with up to 8 Spanning Tree instances
- Supports IEEE 802.1x Access Control Protocol
- Port-Based Access Control
- MAC-Based Access Control
- Guest VLAN
- Supports Quality of Service (QoS)
- Input Bandwidth Control from 64Kbps to 1Gbps (in 64Kbps steps)
- Four Priority Queues per port
- Per-port and per-queue Average and Peak Packet Rate control
- Scheduling supports Strict Priority (SP) and Weighted Fair Queuing (WFQ)
- IEEE 802.1p/Q and IPv4 DSCP Remarking
- Priority decision based on Port, 802.1Q VLAN tag PRI, IPv4/IPv6 DSCP, and ACL rules
- Supports RFC MIB Counter
- MIB-II (RFC 1213)
- Ethernet-Like MIB (RFC 3635)
- Interface Group MIB (RFC 2863)
- RMON (RFC 2819)
- Bridge MIB (RFC 1493)
- Bridge MIB Extension (RFC 2674)
- Security Filtering
- Disable learning for each port
- Disable learning-table aging for each port
- Drop unknown DA for each port
- Broadcast/Multicast/Unknown DA storm control protects system from attack by hackers
- Each port supports 3 parallel LED outputs
- Supports EEPROM SMI Slave interface to access configuration register
- Supports 2048-byte EEPROM space for configuration
- 25MHz crystal or 3.3V OSC input
- Low Power consumption < 500mW/port
- 0.13μm CMOS process
- RTL8366S: LQFP 164-pin E-PAD package RTL8366SR: LQFP 216-pin E-PAD
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