The Realtek RTL8187SE is a low-profile highly integrated cost-effective Single-Chip Wireless LAN network interface controller that integrates a Wireless LAN MAC, a baseband processor, and 2.4GHz RF onto one chip. It provides a PCI Express bus controller, and full compliance with IEEE 802.11 and IEEE 802.11b/g specifications. It also complies with WMM, 802.11e, and CCX specifications.
To reduce protocol overhead, the RTL8187SE supports Short InterFrame Space (SIFS) burst mode to send packets back-to-back. A protection mechanism prevents collisions among 802.11b nodes.
Direct Sequence Spread Spectrum (DSSS), Complementary Code Keying (CCK), and Orthogonal Frequency Division Multiplexing (OFDM) baseband processing are implemented to support all IEEE 802.11b, and 802.11g data rates. Differential phase shift keying modulation schemes, DBPSK and DQPSK with data scrambling capability, are available, along with complementary code keying to provide data rates of 1, 2, 5.5, and 11Mbps, with long or short preamble. A high-speed Fast Fourier Transform (FFT)/Inverse Fast Fourier Transform (IFFT), combined with BPSK, QPSK, 16QAM and 64QAM modulation of the individual sub-carriers, provides data rates of 6, 9, 12, 18, 24, 36, 48 and 54Mbps, with rate-compatible punctured convolutional coding with a coding rate of 1/2, 2/3, and 3/4.
An enhanced signal detector, an adaptive frequency domain equalizer, and a soft-decision Viterbi decoder are built-in to alleviate severe multipath effects. Efficient IQ-imbalance calibration, DC offset, phase noise, frequency offset, and timing offset compensation reduce radio frequency front-end impairments. Selectable digital transmit and receive FIR filters are provided to meet the requirements of transmit spectrum masks, and to reject adjacent channel interference, respectively. Both in the transmitter and receiver, programmable scaling in the digital domain trades the quantization noise against the increased probability of clipping. Robust signal detection, symbol boundary detection, and channel estimation perform well at the minimum sensitivity.
The RTL8187SE supports fast receiver Automatic Gain Control (AGC) and antenna diversity functions, and an adaptive transmit power control function to obtain better performance in the analog portions of the transceiver. It also has on-chip digital-to-analog converters and analog-to-digital converters for analog I and Q inputs and outputs, transmit TSSI and receiver RSSI inputs, and transmit and receiver AGC outputs.
It supports Advanced Configuration Power management Interface (ACPI), Legacy PCI power management, and PCI Express power management for modern operating systems that are capable of Operating System directed Power Management (OSPM). PCI MSI (Message Signaled Interrupt) function and PCI Express Device Serial Number Capability are also supported.
In addition to the ACPI feature, the RTL8187SE also supports remote wake-up (including AMD Magic Packet and Microsoft® wake-up frame) in both ACPI and APM environments. To support Wake on Wireless LAN from a deep power down state (e.g., D3cold, i.e. main power is off and only auxiliary power exists), the auxiliary power source must be able to provide the needed power. When auxiliary power is applied and the main power remains off, the RTL8187SE is ready and waiting for a Magic Packet or wake-up frame to wake the system up.
The RTL8187SE supports an enhanced link list descriptor-based buffer management architecture, which is an essential part of a design for a modern network interface card. It contributes to lowering CPU utilization. Also, the RTL8187SE features inter-connect PCI Express technology. PCI Express is a high-bandwidth, low pin count, serial, interconnect technology that offers significant improvements in performance over conventional PCI and also maintains software compatibility with existing PCI infrastructure. Support is also provided for Multiple BSSID, Adjustable fallback steps and fallback rates during auto rate fallback, TX Power Tracking, Enhanced three-wire mechanism, Parallel Control Interface between Baseband and RF, and Bluetooth coexistence.
The RTL8187SE keeps network maintenance costs low and eliminates usage barriers. The RTL8187SE is highly integrated and requires no ‘glue’ logic or external memory.
- 64-Pin QFN with ‘Green’ package
- State machine implementation without external memory (RAM, flash) requirement
- Complies with IEEE 802.11b/g standards
- Supports descriptor-based buffer management
- Integrated Wireless LAN MAC and Direct Sequence Spread Spectrum/OFDM Baseband Processor in one chip
- Enhanced signal detector, adaptive frequency domain equalizer, and soft-decision Viterbi decoder to alleviate severe multipath effects
- Processing Gain compliant with FCC
- On-Chip A/D and D/A converters for I/Q Data, AGC, and Adaptive Power Control
- Supports both transmit and receive Antenna Diversity
- Data rates of 1, 2, 5.5, 6, 9, 11, 12, 18, 24, 36, 48, and 54Mbps
- Supports 40MHz OSC as the internal clock source. The frequency deviation of the OSC must be within 25ppm on IEEE 802.11g
- PCI Express bus controller
- Complies with PCI Express 1.1 and PCI Express Mini Card Electromechanical Specification Revision 1.1
- PCI power management Revision 1.2
- Supports PCI Express Active State Power Management (ASPM)
- Provides PCI Express bus data transfers and PCI Express memory space or IO space mapped data transfers of the RTL8187SE’s operational registers
- Supports ACPI (Rev 1.0, 1.0b, 2.0)
- Supports Wake-On-WLAN (WoWLAN) function and remote wake-up (Magic Packet and Microsoft® wake-up frame)
- Supports auxiliary power auto-detect, and sets the related capability of power management registers in PCI Express configuration space
- IEEE 802.11g protection mechanisms for both RTS/CTS and CTS-to-self
- Burst-mode support for dramatically enhanced throughput
- DSSS with DBPSK and DQPSK, CCK modulations and demodulations supported with long and short preamble
- OFDM with BPSK, QPSK, 16QAM and 64QAM modulations and demodulations supported with rate compatible punctured convolutional coding with coding rate of 1/2, 2/3, and 3/4
- Efficient IQ-imbalance calibration, DC offset, phase noise, frequency offset and timing offset compensation reduce analog front-end impairments
- Selectable digital transmit and receiver FIR filters provided to meet transmit spectrum mask requirements and to reject adjacent channel interference
- Programmable scaling both in transmitter and receiver to trade quantization noise against the increased probability of clipping
- Fast receiver Automatic Gain Control (AGC) & antenna diversity functions
- Adaptive transmit power control function
- Complies with WMM, 802.11e, and CCX specifications
- Complies with 802.11i and 802.11j specifications
- Hardware-based IEEE 802.11i encryption/decryption engine, including 64-bit/128-bit WEP, TKIP, and AES
- Supports Wi-Fi alliance WPA and WPA2 security
- Supports a 32-bit general-purpose timer
- Contains two large independent transmit and receive FIFO buffers
- Advanced power saving mode when the LAN and wakeup function are not used
- Uses 93C46 (64*16-bit EEPROM) or 93C56 (128*16-bit EEPROM) to store resource configuration and ID parameter data
- LED pins for various network activity indications
- Nine GPIO pins supported
- Supports digital loopback capability on both ports
- Flexible RF transceiver interface for different RF transceiver applications
- Built-in 3.3V to 1.8V regulator
- 3.3V power supply required
- 0.18μm CMOS process