The RTL8363SB-CG is an LQFP128, high-performance 2+2-port 10/100/1000M Ethernet switch. It features low-power integrated dual-port Gigabit PHYs that support 1000Base-T, 100Base-TX, and 10Base-T.
For specific applications, the RTL8363SB supports two extra interfaces that can be configured as GMII/RGMII/MII interfaces. The RTL8363SB integrates all the functions of a high-speed switch system; including SRAM for packet buffering, non-blocking switch fabric, and internal register management into a single CMOS device. Only a 25MHz crystal is required; an optional EEPROM is offered for internal register configuration.
The embedded packet storage SRAM in the RTL8363SB features superior memory management technology to efficiently utilize memory space. The RTL8363SB integrates a 2K-entry look-up table with a 4-way XOR Hashing algorithm for address searching and learning. The table provides read/write access from the EEPROM Serial Management Interface (SMI), Media Independent Interface Management (MIIM), or SPI Interface. Each of the entries can be configured as a static entry. Normal entry aging time is between 200 and 400 seconds. Eight Filtering Databases are used to provide Independent VLAN Learning and Shared VLAN Learning (IVL/SVL) functions.
The Extension GMAC0 and Extension GMAC1 of the RTL8363SB implement dual GMII/RGMII/MII interfaces. These interfaces could be connected to an external PHY, MAC, CPU, or RISC for specific applications. In router applications, the RTL8363SB supports Port VID (PVID) for each port to insert a PVID in the VLAN tag on egress. When using this function, VID information carried in the VLAN tag will be changed to PVID.
Note: The RTL8363SB Extra Interface (Extension GMAC0 and Extension GMAC1) supports:
Dual-Port Gigabit Media Independent Interface (GMII)
Dual-Port Reduced Gigabit Media Independent Interface (RGMII)
Dual-Port Media Independent Interface (MII)
The RTL8363SB supports standard 802.3x flow control frames for full duplex, and optional backpressure for half duplex. It determines when to invoke the flow control mechanism by checking the availability of system resources, including the packet buffers and transmitting queues. The RTL8363SB supports broadcast/multicast output dropping, and will forward broadcast/multicast packets to non-blocked ports only. For IP multicast applications, the RTL8363SB supports IPv4 IGMPv1/v2/v3 and IPv6 MLDv1/v2 snooping.
In order to support flexible traffic classification, the RTL8363SB supports 64-entry ACL rule check and multiple actions options. Each port can optionally enable or disable the ACL rule check function. The ACL rule key can be based on packet physical port, Layer2, Layer3, and Layer4 information. When an ACL rule matches, the action taken is configurable to Drop/Permit/Redirect/Mirror, change priority value in 802.1q/Q tag, and rate policing. The rate policing mechanism supports from 8Kbps to 1Gbps (in 8Kbps steps).
In Bridge operation the RTL8363SB supports 16 sets of port configurations: disable, block, learning, and forwarding for Spanning Tree Protocol and Multiple Spanning Tree Protocol. To meet security and management application requirements, the RTL8363SB supports IEEE 802.1x Port-based/MAC-based Access Control. For those ports that do not pass IEEE 802.1x authentication, the RTL8363SB provides a Port-based/MAC-based Guest VLAN function for them to access limited network resources. A 1-set Port Mirroring function is configured to mirror traffic (RX, TX, or both) appearing on one of the switch’s ports. Support is provided on each port for multiple RFC MIB Counters, for easy debug and diagnostics.
To improve real-time and multimedia networking applications, the RTL8363SB supports eight priority assignments for each received packet. These are based on (1) Port-based priority; (2) 802.1p/Q VLAN tag priority; (3) DSCP field in IPv4/IPv6 header; and (4) ACL-assigned priority. Each output port supports a weighted ratio of eight priority queues to fit bandwidth requirements in different applications. The input bandwidth control function helps limit per-port traffic utilization. There is one leaky bucket for average packet rate control for each queue of all ports. Queue scheduling algorithm can use Strict Priority (SP) or Weighted Fair Queue (WFQ) or mixed.
The RTL8363SB provides a 4K-entry VLAN table for 802.1Q port-based, tag-based, and protocol-based VLAN operation to separate logical connectivity from physical connectivity. The RTL8363SB supports four Protocol-based VLAN configurations that can optionally select EtherType, LLC, and RFC1042 as the search key. Each port may be set to any topology via EEPROM upon reset, or EEPROM SMI Slave after reset.
In router applications, the router may want to know the input port of the incoming packet. The RTL8363SB supports an option to insert a VLAN tag with VID=Port VID (PVID) on each egress port. The RTL8363SB also provides an option to admit VLAN tagged packets with a specific PVID only. If this function is enabled, the RTL8363SB will drop all non-tagged packets and packets with an incorrect PVID.