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Multi-Layer Managed 8*10/100M + 2*10/100/1000M-Port Switch Controller
General Description

The RTL8330M is a new generation 8-port FE switch controller with embedded 8-port FE PHYs provided via a 55nm CMOS process in an LQFP-216 E-PAD package. The RTL8330M also supports 1 pair of RSGMII or 2 pairs of SGMII/1000Base-X/100Base-FX.

The RTL8330M has an embedded 500MHz MIPS-4KEc CPU that supports a 32MByte SPI flash (max.). The Memory interface supports DDR1/DDR2/DDR3. Two 16C550 compatible UARTs are integrated for low speed serial data, and one E-JTAG is supported for on-chip debugging.

There are 8K entries in the 4-way hash L2 table for MAC address learning and searching. The RTL8330M supports two hash algorithms. An independent 512-entry Multicast table supports Layer 2 and IP multicast functions.

The RTL8330M have a 4K-entry VLAN table for 802.1Q port-based, protocol-and-port-based, 802.1Q-based, IP-subnet-based, and ACL Rules-based VLAN operation to separate logical connectivity from physical connectivity. Support is provided for IVL (Independent VLAN Learning), SVL (Shared VLAN Learning), and IVL/SVL (both Independent and Shared VLAN Learning) for flexible network topology architecture. The RTL8330M supports a 1.5K-entry Access Control List (ACL) that parses various protocol packet types and performs configurable actions, e.g., Permit/Drop, redirect, and traffic policing.

The RTL8330M supports per-port ingress/egress bandwidth control and per-queue egress bandwidth control. It has 8 physical queues in each port.

The RTL8330M provides three types of packet scheduling; SP (Strict Priority), WFQ (Weighted Fair Queuing), and WRR (Weighted Round Robin). Each queue provides a leaky-bucket to shape the incoming traffic into the average rate behavior.

Port-based 802.1X and MAC-based 802.1X authentication prevent unauthorized users from accessing internal servers. The RTL8330M supports port isolation to enhance port security. The RTL8330M also supports a 4-set port mirror configuration to mirror ingress and egress traffic. For network management purposes, complete MIB counter support reflects the switch status in real time. Support is provided for link aggregation to increase link redundancy, and increase linear bandwidth.

The RTL8330M adopts advanced technologies such as Realtek Cable Test (RTCT), Automatic loop detection and prevention (RLPP/RLDP), Attack Prevention, and MAC Address Learning Constraints. The RTL8330M supports Energy Efficient Ethernet (EEE). 

Hardware Interface
  • 8-port FE +2-port Gigabit wire speed forwarding capability
  • Supports 8-port internal Fast Ethernet PHYs
  • Support 1 pair of RSGMII or 2 pairs of SGMII/1000Base-X/100Base-FX
  • Flexible Interfaces for Internal or External CPU
    • Serial/Dual I/O mode 32MB SPI Flash
    • Up to 128MB DDR1/DDR2 and 256MB DDR3 for internal MIPS-4KEc
  • Embedded MIPS-4KEc with MMU
    • MIPS32 instruction set and 5-stage pipeline
    • 500MHz CPU clock rate
    • 16KByte I-Cache and 16KByte D-Cache
    • Built-in 128KByte SRAM
    • 32 Translation Look-aside Buffer (TLB) entries
    • Two UART interfaces to control the internal CPU via a Command Line Interface (CLI)
  • EJTAG interface
  • EEPROM, I2C, and SPI interface for external CPU to access internal registers
L2 VLAN Function
  • IVL, SVL, and IVL/SVL
  • IEEE 802.1Q VLAN
    • 4K-entry VLAN Table
    • Port-based VLAN
    • Port-and-protocol-based VLAN
    • ACL-based VLAN
    • Supports up to 64 spanning tree instances for MSTP (IEEE 802.1s), RSTP, and STP
  • Flexible Q-in-Q and VLAN Tag function
L2 MAC Function
  • 4.1 Mbit SRAM Packet Buffer
  • Packet length of 10KB
  • 8K-entry L2 MAC table with 4-way hashing algorithm
  • Independent 512-entry L2/IP Multicast table for multicast function
  • 2-hash algorithm selection for L2 table searching/learning
  • Aging timer range from 0.2s to 1600000s
  • IGMPv1/2/3 and MLDv1/2 snooping
  • Reserved Multicast Addresses processing
  • Limited learned L2 MAC entry on each port and each VLAN
L2 Miscellaneous Functions
  • Broadcast, multicast, unknown- multicast, and unknown-unicast packet storm control
  • IEEE 802.1x; needs software support
  • Traffic Mirroring
    • Supports 4-sets of port mirrors
    • Flow-based mirror function
    • RSPAN function for remote mirroring
  • Supports Link Aggregation (IEEE 802.3ad) for 8 groups of link aggregators with up to 8 ports per-group
  • Port isolation function to enhance port security
  • Attack Prevention
  • Supports Automatic loop detection and isolation (RLPP/RLDP)
Access Control List (ACL) Function
  • 1.5K-entry ACL table
  • L2/L3/L4 format (e.g., DMAC, SMAC, and Ether-Type)
  • IPv6 Parsing
  • Per-flow traffic policing
  • 16-entry VID range checking
  • 8-entry IPv4 or 2-entry IPv6 range checking
  • 64 leaky-buckets for flow traffic policing; in 16Kbps steps up to 1Gbps maximum
  • 256 log counters to enhance MIB count functionality
  • Supports multiple action
  • Supports L3 Unicast Routing, 512 next hop MAC Support
QoS Functions
  • 8 physical queues per port
  • Strict Priority (SP) and Weighted Fair Queue (WFQ), Weighted Round Robin (WRR) packet scheduling
  • QoS remarking for 802.1p and DSCP (includes IPv4/IPv6)
  • Supports average packet rate control leaky-bucket per queue, in 16Kbps steps up to 1Gbps maximum
  • Ingress port bandwidth control, in 16Kbps steps up to 1Gbps maximum
  • Egress port bandwidth control, in 16Kbps steps up to 1Gbps maximum
EAV, 1588v2

Cable Diagnostics (RTCT)

IEEE 802.3az Energy Efficient Ethernet (EEE)

MIB Functions
  • Ethernet-like MIB (RFC 3635)
  • Interface Group MIB (RFC 2863)
  • RMON (RFC 2819)
  • Bridge MIB (RFC 1493)
  • Bridge MIB Extension (RFC 2674)
  • 55nm CMOS process
  • 3.3V/1.1V dual power input
  • LQFP216 E-PAD package
  • Managed 8-port FE + 2-port SGMII/1000Base-X Switch


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