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Multi-Layer Managed 24*10/100M + 4*10/100/1000M-Port Switch Controllers
General Description

The RTL8328M/RTL8328S is a highly integrated Layer 2/Layer 4 management switch that offers 24-port Fast Ethernet MAC, 5-port Gigabit Ethernet MAC, 16-port Fast Ethernet PHY, and embedded 400MHz MIPS-4KEc processor. The RTL8328M/RTL8328S also provides three SerDes interface channels to connect to external PHY or fiber transceivers.

The Memory interface of the RTL8328M/RTL8328S supports SDR/DDR SDRAM and SPI Flash.

The embedded 400MHz MIPS-4KEc CPU supports 8-bit 256M-Byte DDR SDRAM, 16-bit data bus 256M-Byte DDR SDRAM, 16-bit data bus 256M-Byte SDR SDRAM (max), and 32M-Byte serial I/O, dual I/O, quad I/O SPI Flash (max).

There are 16K entries in the 4-way hash L2 table for MAC address learning and searching. The RTL8328M/RTL8328S supports two hash algorithms, and has a 64-entry CAM. An independent Multicast table supports Layer 2 and IP Multicast functions:

·       RTL8328S supports 512-entry Multicast table

·       RTL8328M supports 1K-entry Multicast table

The RTL8328M/RTL8328S has a 4K-entry VLAN table for 802.1Q port-based, protocol-and-port-based, 802.1Q-based, IP-subnet-based, and ACL rules-based VLAN operation to separate logical connectivity from physical connectivity. Support is provided for IVL (Independent VLAN Learning), SVL (Shared VLAN Learning), and IVL/SVL (Both Independent and Shared VLAN Learning) for flexible network topology architecture. The RTL8328M/RTL8328S also offers a flexible Q-in-Q function.

The ACL (Access Control List) function provides features such as parsing various protocol packet types and performing configurable actions, e.g., Permit/Drop, Redirect, and traffic policing.

·       RTL8328S supports 512-entry ACL and 512 flow counters

·       RTL8328M supports 2K-entry ACL and 1K flow counters

The RTL8328M/RTL8328S supports per-port ingress/egress bandwidth control and per-queue egress bandwidth control. It has 8 physical queues in each port. The RTL8328M/RTL8328S provides three types of packet scheduling, including SP (Strict Priority), WFQ (Weighted Fair Queuing), and WRR (Weighted Round Robin). Each port and each queue provide a rate limit function.

Port-based 802.1X and MAC-based 802.1X authentication prevent unauthorized users from accessing internal servers. The RTL8328M/RTL8328S supports port isolation to enhance port security. The RTL8328M/RTL8328S also supports a 4-set port mirror configuration to mirror ingress and egress traffic. For network management purposes, complete MIB counter support reflects the switch status in real time. Support is provided for link aggregation to increase link redundancy, and increase linear bandwidth.

The RTL8328M/RTL8328S adopts advanced technologies such as IEEE 802.3az Energy Efficient Ethernet (EEE), Realtek Cable Tester (RTCT), Unidirectional Link Detection (UDLD), Attack Prevention, and MAC Address Learning Constraints.

    Hardware Interface
  • 24-port 10/100M and 4-port Gigabit wire speed forwarding capability
    • Supports 16-port internal 10/100M Ethernet PHYs
    • RTL8328M/RTL8328S supports 2 pairs of 2.5Gbps RSGMII to external 4-port 10/100/1000M Ethernet PHY
    • RTL8328M/RTL8328S supports 2 ports GMII/RGMII/MII to external 2-port 10/100/1000M Ethernet PHY
  • Flexible Interfaces for Internal CPU
    • 8-bit and 16-bit data bus 256MByte DDR SDRAM interface for internal MIPS-4KEc
    • 16-bit data bus 256MByte SDR SDRAM interface for internal MIPS-4KEc
    • 32MByte serial I/O, dual I/O, or quad I/O SPI Flash interface for internal MIPS-4KEc
  • Embedded MIPS-4KEc with MMU
    • MIPS32 instruction set and 5-stage pipeline
    • 400MHz CPU clock rate
    • 16KByte I-Cache and 16KByte D-Cache
    • 32 Translation Look-aside Buffer (TLB) entries
    • Two UART interfaces to control the internal CPU via a Command Line Interface (CLI)
  • EEPROM SMI interface for external CPU to access internal register
  • EJTAG interface
    L2 VLAN Function
  • IVL, SVL, and IVL/SVL
  • IEEE 802.1Q VLAN
    • 4K-entry VLAN Table
    • Port-based VLAN
    • Port and protocol-based VLAN
    • ACL-based VLAN
    • Supports up to 128 spanning tree instances for MSTP (IEEE 802.1s), RSTP, and STP
  • Flexible Q-in-Q and VLAN Tag function

    Cable Diagnostics (RTCT)

    IEEE 802.3az Energy Efficient

    Ethernet (EEE)  L2 MAC Function
  • 2.5Mbit SRAM Packet Buffer
  • Packet length up to 2KB (FE port), 9KB (Giga port)
  • 16K-entry L2 MAC table with 4-way hashing algorithm
  • RTL8328M supports independent 1K entry, and RTL8328S supports 512 entry L2/IP Multicast table for multicast function
  • 2-hash algorithm selection for L2 table searching/learning
  • Aging timer range from 0.6s to 1,500,000s
  • IGMPv1/2/3, and MLDv1/2 snooping
  • Reserved Multicast Addresses processing
  • Limited learned L2 MAC entry on each port and each VLAN

    L2 Miscellaneous Functions
  • Broadcast, multicast, unknown- multicast, and unknown-unicast packet suppression control
  • Supports IEEE 802.1X
    • Port-based 802.1X
    • MAC-based 802.1X
    • Guest VLAN
  • Traffic Mirroring
    • 4-sets of port mirrors
    • Flow-based mirror function
    • RSPAN function for remote mirroring
    • sFlow for network diagnosis
  • Link Aggregation (IEEE 802.3ad) for 8 groups of link aggregators with up to 8 ports per-group
  • Port isolation function to enhance port security
  • Supports Field selector
  • Supports Pattern matching
  • Supports Range Check
  • UniDirectional Link Detection (UDLD)

    Access Control List (ACL) Functions
  • RTL8328M supports 2K-entry ACL table
  • RTL8328S supports 512-entry ACL table
  • L2/L3/L4 format (e.g., DMAC, SMAC, and Ether-Type)
  • 64-Byte shared Content Based Filtering
  • Per-flow traffic policing
  • Port/VID/IP range operation
  • 32-entry VID range checking
  • 64-entry IPv4 or 16-entry IPv6 range checking
  • 256 leaky-buckets for flow traffic policing, in 16Kbps steps up to 1Gbps maximum
  • RTL8328M supports 1K log counters, and the RLT8328S supports 512 log counters, to enhance MIB count functionality
  • Supports action to Drop/Permit/ Redirect/Copy to CPU/Mirror/ Logging/Policing/New Inner-VID/New Outer-VID/Remove tag/Insert tag/Keep Tag/Modify tag/Routing/DSCP Priority Remarking/Rule Match indication

    QoS Functions
  • 3-level Weighted Tail Drop (WTD) and Weighted Random Early Detection (WRED)
  • 8 priority queues
  • Strict Priority (SP) and Weighted Fair Queue (WFQ), Weighted Round Robin (WRR) packet scheduling
  • Supports average packet rate control leaky-bucket per queue, in 16Kbps steps up to 1Gbps maximum
  • Ingress port bandwidth control, in 16Kbps steps up to 1Gbps maximum
  • Egress port bandwidth control, in 16Kbps steps up to 1Gbps maximum
  • Priority & DP remarking and DSCP remarking (includes IPv4/IPv6)

    Denial-of-Service attack (DoS attack) Prevention

    MIB Functions
  • Ethernet-like MIB (RFC 3635)
  • Interface Group MIB (RFC 2863)
  • RMON (RFC 2819)
  • Bridge MIB (RFC 1493)
  • Bridge MIB Extension (RFC 2674)

  • 0.11µm CMOS process
  • 3.3V/1.2V dual power input
  • EDHS-PBGA388 package
  • Layer 2 Managed 24*10/100M+4G Switch
  • 24*10/100M with Dual MII/RGMII/GMII MDU System


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